It is known that many interconnection networks used in parallel processors or other systems handling large numbers of items in parallel follow a common construction rule. Commonly known networks of this type are the flip network, bitonic sort network, the Omega network, the indirect binary n-cube, the butterfly network, and the Benes network. It is known that a small network can be put on a single printed circuit board, but that large networks must be spread across several boards. When this occurs, the wiring interconnections between boards often result in what is termed a rat's nest. The rat's nest results from the fact that wire interconnections cross each other, rather than running parallel to each other.
It is most desirable that the interconnections between the various boards maintaining portions of a large network be parallel to each other such that crisscrossing of wires is minimized. The undesirable feature of the rat's nest is, at the least, the substantial difficulty in tracing wire interconnections, coupled with the complications involved in removing or replacing wires.